Arteris Connected Blog

FlexNoC Version 3 available now!

Posted by Kurt Shuler on Wed, Apr 08, 2015 @ 12:11 PM

We announced FlexNoC Version 3 today!

Our primary engineering goal with this totally new technology release was to increase the productivity of our SoC designer users.

As the size and complexity of our user’s SoC designs increased over the years, it had become increasingly difficult to visualize and optimize a huge design in a single GUI window. In addition, we saw the need to make the FlexNoC user interface adapt to whatever task the user is performing, rather than provide the same access to the many options within FlexNoC.

Under the hood, we increased the performance of all aspects of the product, not just user interface response but also performance modeling and exploration.

Here are the top 3 features in the new FlexNoC Version 3:

  1. Switch-based topology editor – It is now easier to create, characterize and modify large designs while keeping access to the entire SoC topology available within a single view.
  2. Topic- and activity-based user interface – Years of customer feedback and human factors research have resulted in a streamlined interface that makes it easier for SoC architects and designers to perform complex and repetitive tasks.
  3. NoC composition enhancements – Users can more easily break large interconnect designs into smaller modules for implementation by different sub-teams, and can quickly combine separate designs or modules into a single interconnect instance for integration.

NEXT STEPS:

Current customers can upgrade from the current version of FlexNoC to FlexNoC Version 3. Just contact your Arteris sales manager.

For prospective customers, please contact me and we'll get you started!

For more details, please read our press announcement below.

 

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Tags: network-on-chip, SoC design, Arteris FlexNoC

Streamlining Interconnect Integration Accelerates Globally Distributed Design

Posted by Kurt Shuler on Tue, Mar 03, 2015 @ 01:59 PM

Specialized teams find new ways to stitch individual efforts into the SoC fabric.

As system on chip designs grow more complex, it becomes more and more difficult for chip companies to optimize the work of their distributed design teams. While each separate team has an area of expertise and sets their focus on a particular aspect of the SoC, the hard part comes in integrating these individual design efforts together. When something goes wrong and it doesn’t work, the company’s critical time to market advantage starts to slip.

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Tags: SoC design, NoC composition, IP integration

Moore's Law is Dead: Long Live SoC Designers

Posted by Kurt Shuler on Mon, Feb 02, 2015 @ 04:40 PM

Author's note: This article was originally published in Design & Reuse where it has been read by nearly 2,000 engineers and shared by over 100 people.

As the "Free Lunch" Era Closes, Chip Designers Grow in Value by Providing Innovative Ways to Increase Performance and Cut Power Consumption

Let’s face it, Moore’s Law has been the free lunch program of the semiconductor industry. And now that Moore’s Law is dead, how will SoC designers continue to survive?

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Tags: SoC design, moore's law

The Top 35 ISO 26262 acronyms and abbreviations

Posted by Kurt Shuler on Mon, Jan 05, 2015 @ 12:30 PM

A glossary of ISO 26262 abbreviations and acronyms can be a great help to understanding functional safety standards.


INTRODUCTION:

2015-01-05-iso26262-tableOver the last one-and-a-half years that I have been elbow-deep working on the FlexNoC Resilience Package, I’ve been keeping a running list of ISO abbreviations and acronyms that reoccurred in my work, and kept confusing me whenever I performed a “context switch” from working on different projects to working on my functional safety products.

I’ve received feedback that my list is helpful, so I’m publishing it in the hope that it helps you, too. I’ve attempted to explain everything in “plain English” and have referred to the specific “chapter and verse” in the ISO 26262 specification where the term is officially explained (kind of like Bible Study notes!).

Also, for a short explanation of ISO 26262 functional safety certifcation, please see my article, "A Primer On ISO 26262 Certification."

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Tags: functional safety, ISO 26262

A Primer On ISO 26262 Certification

Posted by Kurt Shuler on Fri, Oct 31, 2014 @ 11:23 AM

What does it take to be ISO-compliant, how you get certified, and who exactly makes the standards.

As the electronic processing capabilities of the average car increases, more and more software, semiconductor, and semiconductor IP companies are trying to enter the automotive electronics market. Many of these new entrants have strong backgrounds in consumer electronics or the PC industry, and are new to the unique requirements of the automotive market.

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Tags: functional safety, ISO 26262

‘Hardening’ SoCs For Automotive Market Challenges

Posted by Kurt Shuler on Tue, Sep 30, 2014 @ 11:02 AM

Migrating from mobility into new markets means dealing with new issues such as reliability, security and quality of service.

The semiconductor industry is enamored with the automotive, industrial and medical markets, and many companies are now shifting their focus there. But many mainstream vendors will face challenges entering this market. For those who have traditionally participated in the smart phone or mobility market, I will outline some changes they need to consider to successfully compete in these emerging spaces.

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Tags: ARM, automotive semiconductors, SoC safety, SoC security, SoC QoS

Arteris is hiring: 4 job openings for HW engineers & SW developers!

Posted by Kurt Shuler on Tue, Aug 05, 2014 @ 11:48 AM

Our current office in Campbell is nearly full and we have room for only four more people until we expand our office again. If you are a hardware engineer or software developer, then we want you to consider joining us!

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Tags: software, jobs, software jobs, hardware jobs

What Does It Cost You When Your SoC is Late to Market?

Posted by Kurt Shuler on Fri, Jul 25, 2014 @ 11:44 AM

If your chip is late to market, it is costing you far more than you know.

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Tags: SoC, interconnect IP, interchip connectivity, Late, Market, Cost, chip, design

The Critical Cost of Routing Congestion

Posted by Kurt Shuler on Thu, Jul 17, 2014 @ 02:45 PM

By Jonah Probell, Senior Solutions Architect, Arteris

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Tags: SoC, SoC economics, SoC design, routing congestion, timing closure

Arteris is hiring engineers!

Posted by Kurt Shuler on Fri, May 09, 2014 @ 11:55 AM

You may have noticed from the Arteris LinkedIn company page or our website that we have been hiring. We have three more jobs where we need top people:

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Tags: hardware verification, hardware design, arteris jobs