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Kurt Shuler bio

Kurt Shuler Arteris Intel TI MIT USAFAKurt Shuler is the VP of marketing at Arteris. 

He has held senior roles at Intel, Texas Instruments, ARC International and two startups, Virtio and Tenison. Before working in high technology, Kurt flew as an air commando in the U.S. Air Force Special Operations Forces.

Kurt earned a B.S. in Aeronautical Engineering from the U.S. Air Force Academy and an MBA from the MIT Sloan School of Management.

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What Does It Cost You When Your SoC is Late to Market?

  
  
  

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If your chip is late to market, it is costing you far more than you know.

The Critical Cost of Routing Congestion

  
  
  

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By Jonah Probell, Senior Solutions Architect, Arteris

Arteris is hiring engineers!

  
  
  

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You may have noticed from the Arteris LinkedIn company page or our website that we have been hiring. We have three more jobs where we need top people:

Arteris Emerges Strong in 2014 As Semiconductor Markets Diversify

  
  
  

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National Hockey League Hall of Famer Wayne Gretzky famously once said, “A good hockey player plays where the puck is. A great hockey player plays where the puck is going to be.”

For 2014, the team at Arteris is convinced that FlexNoC interconnect fabric IP will play a greater role in the most advanced System-on-Chip (SoC) projects in the industry. To paraphrase the Great One, Arteris is not only playing where the puck is – mobility – but will play where the semiconductor industry is going to be – wearables and the Internet of Things.

SemiEngineering: The Uncertain Future Of Fabless Semis

  
  
  

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Ann Steffora Mutschler wrote this provocative article at Semiconductor Engineering. I am reprinting it here for your convenience with the permission of Semiconductor Engineering. Kevin Kranen's points regarding software driving the hardware are very important for our industry to internalize.

Wake Up, Semi Industry: System OEMs Might Not Need You

  
  
  

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The rules are changing for the semiconductor industry and traditional vendors had better find ways to be more competitive or they will find themselves missing out on some of the most exciting, high-growth markets.

Divide & Conquer: Dispersed global design teams need NoC fabric IP

  
  
  

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It’s no surprise that most corporate system-on-chip (SoC) design teams are dispersed throughout the world, with different functional teams often located in different countries and continents. For example, we have many customers whose SoC architecture is defined in the United States, but subsystems such as graphics and signal processing are designed elsewhere. Companies choose this "divide and conquer" approach in the hopes of reducing design costs without affecting time to market.

Asymmetric Multiprocessing with Heterogeneous Architectures: Use the Best Core for the Job

  
  
  

Often, the term “multiprocessing” is associated with tightly-coupled symmetric multiprocessing (SMP) architectures, due in large part to SMP’s prevalence in high-performance computing, x86/x64 servers, and PCs. Unfortunately, SMP’s incremental performance scaling for most applications decreases significantly with increasing numbers of cores. This lack of scalability has prompted many processor companies to avoid purely SMP solutions for their mobile and consumer electronics applications. Instead, they have implemented asymmetric multiprocessing (AMP) architectures to make more efficient use of silicon.

The SoC Interconnect Fabric: A Brief History

  
  
  

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The high functional integration of system-on-chip designs today is driving the need for new technological approaches in semiconductor design. Anyone who owns a Samsung Galaxy S4, HTC One or comparable smartphone can see the benefits of integrating onto one chip all the computing functions that were traditionally separate, discrete chips on a PC computer motherboard. For next-generation devices, developers are driving even greater computing power, higher resolution graphics, and improved media processing into the integrated SoCs that enable these systems. This high level of integration is causing on-chip communications and transaction handling to become a system constraint within the SoC, limiting the achievable performance of SoCs no matter how optimized the individual CPU, GPU and other IP blocks.

DAC Is Dead? Long Live DAC!

  
  
  

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I have long decried the declining attendance at the ACM/EDAC/IEEE Design Automation Conference (DAC), especially in regard to this trend’s adverse effect on continuing professional education (CPE) opportunities for our industry’s engineers. (See my May 2011 article, “The Trouble With Tradeshows, for more.) In fact, for those of you who know me personally, I have sometimes quite cynically referred to DAC as our, “EDA high school reunion,” implying that little business is conducted there and that DAC is simply an annual opportunity for us to see who from our past got fat, bald, and/or divorced. (I’m 2 out of 3 in that list. E-mail me if you know which and I will buy you a beer.)

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