Arteris Connected Blog

It’s official: The great IP land grab has begun.

The process actually has been taking place gradually, but has accelerated with Imagination Technologies’ acquisition of MIPS last year and, most recently, Cadence’s acquisition of Tensilica. For makers of semiconductors, four competing IP behemoths are emerging after years of fragmentation within the semiconductor IP industry.

The four big IP players are now ARM, Synopsys, Imagination and Cadence.

I was fortunate to be able to meet with 13 different semiconductor industry analysts from eight different companies over the last two weeks. Our conversations ranged from the current state of the semiconductor industry to future software architecture trends. I want to take this opportunity to thank them once again for the exchange of ideas and the opportunity to learn from them. Here’s a summary of some things I learned, and also some things that surprised me.

Faster IP Integration

As engineers, we view transaction protocols as simply a language to be able to communicate information from one block of system-on-chip (SoC) IP to another block. However, if you look at transaction protocols from an economics framework you see there’s much more to it. With the past interconnect fabrics dominated by crossbars and hierarchal busses, the choice of the IP transaction protocol created a humongous switching cost.

I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year.  But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward.

In September’s article, SMP, Asymmetric Multiprocessing, and the HSA Foundation, I explained why symmetric multiprocessing (SMP) architectures have been popular in PC and server markets, and why heterogeneous or asymmetric multiprocessing (AMP) has been the norm in mobility and consumer electronics markets. I also explained the trends that are leading PC and server markets to adopt heterogeneous architectures and introduced the HSA Foundation’s goal of making heterogeneous core chips easy to program.

Recently, Sonics board member Jim Hogan uploaded some content onto deepchip.com (http://www.deepchip.com/items/0511-06.html) that purports to provide unbiased guidance regarding metrics for evaluating network-on-chip technology and interconnect fabrics. I applaud Jim for his analysis of the metrics one should use to evaluate SoC interconnects.

When we hear the term “multiprocessing,” we often associate it with “symmetric multiprocessing (SMP).” This is because of SMP’s initial prevalence in the high-performance computing world, and now in x86/x64 servers and PCs. However, it’s been known for years that SMP’s ability to scale performance as the number of cores increases is poor.

My purpose in this article is to explain Gartner Research’s Hype Cycle and relate it to the Technology Adoption Lifecycle popularized by Geoffrey Moore’s book, “Crossing the Chasm.”  These two models can be used together to provide a combined picture of market expectations and expected technology adoption rates, but people often get the timeframes and takeaways wrong. So if you’re involved in technology as an engineer, marketer or manager, read on!

We had some very good news at Arteris this week: We made the Inc. 500 list of America's fastest growing companies!