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Kurt Shuler bio

Kurt Shuler Arteris Intel TI MIT USAFAKurt Shuler is the VP of marketing at Arteris. 

He has held senior roles at Intel, Texas Instruments, ARC International and two startups, Virtio and Tenison. Before working in high technology, Kurt flew as an air commando in the U.S. Air Force Special Operations Forces.

Kurt earned a B.S. in Aeronautical Engineering from the U.S. Air Force Academy and an MBA from the MIT Sloan School of Management.

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System-Level Design Arteris CTO interview: Faster IP Integration

  
  
  

Arteris System Level Design

Faster IP Integration

By Ed Sperling
System-Level Design sat down with Laurent Moll, chief technology officer at Arteris, to talk about interoperability, complexity and integration issues. What follows are excerpts of that conversation.

SLD: What’s the big challenge with IP?


Advanced SoC Interconnect IP Enables Greater Flexibility in an Era of Consolidation

  
  
  

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I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year.  But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward.

NoC Interconnect Technology Becoming Mainstream

  
  
  

Gartner Semiconductor Hype Cycle 2011

Gartner analyst Jim Tully’s assessment that network on chip (NoC) technology will be “mainstream” in two to five years is an acknowledgement of the technical and commercial success NoC interconnect IP has had in the consumer electronics system on chip (SoC) market over the last couple of years.

NoC is not a Noun

  
  
  

Arteris System Level DesignAs featured in:
Today in the IP and EDA business, I hear “knock” all the time, except people mean “NoC.” It seems everybody wants a NoC, or wants to offer you a NoC. I’m here to tell you that NoC is not a noun.

A network-on-chip is a technology approach that can be used to transfer data and commands in many domains. When people in the IP and EDA businesses say NoC, they are usually referring to the means to control a SoC interconnect fabric, either within a chip, between chips, or both. In short, it is an adjective that describes a type of SoC interconnect solution.

Busses, Crossbars and NoCs: The 3 Eras of SoC Interconnect History

  
  
  

Network on Chip (NoC) SoC AXIToday the processor in your Blackberry or iPhone has more calculating power than a PC did only a decade ago. No surprise here. But how did this happen? What enabled this?

The pat answer of course is “Moore’s law enabled semiconductor designers to cram more transistors into a given area each year, allowing more functions to be added to a chip.”

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