Arteris Connected Blog

Faster IP Integration

As engineers, we view transaction protocols as simply a language to be able to communicate information from one block of system-on-chip (SoC) IP to another block. However, if you look at transaction protocols from an economics framework you see there’s much more to it. With the past interconnect fabrics dominated by crossbars and hierarchal busses, the choice of the IP transaction protocol created a humongous switching cost.

I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year.  But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward.

Recently, Sonics board member Jim Hogan uploaded some content onto deepchip.com (http://www.deepchip.com/items/0511-06.html) that purports to provide unbiased guidance regarding metrics for evaluating network-on-chip technology and interconnect fabrics. I applaud Jim for his analysis of the metrics one should use to evaluate SoC interconnects.

A network-on-chip is a technology approach that can be used to transfer data and commands in many domains. When people in the IP and EDA businesses say NoC, they are usually referring to the means to control a SoC interconnect fabric, either within a chip, between chips, or both. In short, it is an adjective that describes a type of SoC interconnect solution.

I hope my title doesn't sound too condescending, and I apologize for stealing Bill Clinton's 1992 campaign slogan, but it's apparent to me that a lot of the talk on the Internet about the Chinese Tianhe-1A supercomputer is sour grapes.

The pat answer of course is “Moore’s law enabled semiconductor designers to cram more transistors into a given area each year, allowing more functions to be added to a chip.”