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Kurt Shuler bio

Kurt Shuler Arteris Intel TI MIT USAFAKurt Shuler is the VP of marketing at Arteris. 

He has held senior roles at Intel, Texas Instruments, ARC International and two startups, Virtio and Tenison. Before working in high technology, Kurt flew as an air commando in the U.S. Air Force Special Operations Forces.

Kurt earned a B.S. in Aeronautical Engineering from the U.S. Air Force Academy and an MBA from the MIT Sloan School of Management.

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Interchip Connectivity: HSIC, UniPro, HSI, C2C, LLI...oh my!


There has been a lot of confusion about the different standards for interchip connectivity, with many hardware developers of consumer electronics and mobile computing systems-on-chip wondering what to use. As an interconnect IP provider, I struggle with this every day when working with our customers. I wrote this article to share what I have learned.

[Note: Table below was update 10 April 2012.]

LLI C2C standards table resized 600

Why interchip connectivity?

The simplest answer is, “Because I want to connect two SoCs together on a PCB with as few traces and as little power consumption as possible.”

But there are other considerations:

  1. Are you connecting your own chips, or chips from other vendors? If from other vendors you will need to research the standards used in those chips. You’ll also need to make sure you match voltages and timings.
  2. How many pins do you have available? Some standards like USB HSIC and MIPI LLI only need 2 pins, while others like C2C require at least 24. Application processors are usually more pin-constrained than companion chips or mobile phone modems.
  3. How much power can you burn? Only C2C does not require a PHY. USB HSIC still requires a PHY even though it doesn’t require a full transceiver setup like a regular USB connection. MIPI HSI and LLI also require a PHY. Applications processors can usually accommodate another PHY, but companion chips like mobile phone modems or LTE coprocessors may be area or power limited.
  4. Do you want to share memory between the two chips? C2C and MIPI LLI are very low latency interfaces that are fast enough for a mobile phone modem or companion chip to share an application processor’s RAM and to maintain enough read throughput and low latency for cache refills. This enables remote configuration and memory mapped transfers as if the two chips were a single chip. 
  5. What is the impact on your software ? C2C and LLI are memory-mapped interfaces that only require software intervention to set them up: The actual data transfers do not require any software driver intervention, and one of the chips does not require a driver at all.

    What are the interchip connectivity standards?

    USB 2.0 High Speed Inter Chip (HSIC)

    HSIC was adopted as a standard by the USB Implementers Forum in 2007. It is a chip-to-chip variant of USB 2.0 that eliminates conventional USB PHYs. The HSIC PHY uses about 50% less power and 75% less area compared to traditional USB 2.0 PHYs. HSIC uses 2 signals at 1.2v and has a throughput of 480Mbit/sec using 240MHz DDR signaling. Maximum PCB trace length for HSIC is 10cm. It does not have low enough latency to support RAM memory sharing between two chips.

    MIPI High-speed Synchronous Serial Interface (HSI) v1.0

    HSI was created in 2003 and is now managed by the MIPI Alliance. It is the granddaddy of mobile phone inter-chip interconnects and is still present leading SoCs like TI’s OMAP 5 platform. HSI operates at 1.2 or 1.8 volts and has throughout of 200 Mbit/sec. It does not have low enough latency to support RAM memory sharing between two chips.

    MIPI UniPro/UniPort v1.4

    The UniPro specification was first released in 2007. UniPort is simply UniPro combined with a MIPI D-PHY or M-PHY. A 2-wired differential D-PHY or M-PHY interface supports a maximum data transfer rate of 800 Mbit/sec, but the UniPro data lane is scalable from 1 to 4 lanes for a total throughput of 3.2 Gbit/sec. UniPro is not low latency enough for RAM sharing.

    MIPI Low Latency Interface (LLI)

    The MIPI LLI specification will be released in 2011. Its primary purpose is to allow sufficient performance to enable sharing a DRAM memory between 2 chips for data and programs. The main motivation is electronic bill of materials (eBoM) cost reduction. MIPI LLI requires only 2 or 4 pins but does require a MIPI M-PHY capable of Gear 2 for mobile phone use models. Round trip latency is targeted to be 80 nanoseconds using 8 pins in Gear 3, allowing a mobile phone modem or companion chip to share an application processor’s RAM. This saves a minimum of $2 in device eBoM cost, saves PCB space, and reduces device complexity. Unidirectional throughput is 2.9 Gb/sec per lane using MIPI M-PHY Gear 2.

    C2C Chip-to-Chip

    C2C has been available since 2010 and is a product containing technology from Texas Instruments and Arteris. It was created to allow DRAM memory sharing for reduced eBoM cost through a very low latency interface. C2C does not require a PHY, however, unlike MIPI LLI’s 2 or 4 pin requirement, C2C requires about 30  pins total in a mobile phone use model (16 transmit pins, 8 receive pins, plus clock and power pins). The interface can use existing DDR pads and is LPDDR I/O compliant. Round trip latency is 100ns, allowing a modem or companion chip to share an application processor’s memory. At 100,000 gates, C2C is very small. It requires 1.2 or 1.8 volts and has throughput of 6.4 Gb/sec at 200 MHz DDR speeds and using 16 pins.

    Which interchip connectivity option to choose?

    The decision on what inter-chip connectivity standard to use is dependent upon a product’s specific use cases and requirements, as well as the interfaces available in the companion products with which it will connect. You will need to understand ahead of time whether you require basic connectivity, or whether you require more exotic features like the memory sharing capabilities delivered by C2C and LLI, and how much embedded software impact this will have on your system.

    Keep in mind that the companion chips with which you would like to connect may have different connectivity requirements and roadmaps than your own products. Therefore it is important to coordinate with the organizations that create these companion chips, whether these teams are in your company or external.

    As featured in: Arteris System Level Design


    Hi Kurt,  
    Great summary of the latest inter-connect interfaces. Such comparison is rare to find online.  
    How do you see UFS, eSATA, and SSIC interfaces plays in the same ecosystem? 
    Posted @ Tuesday, August 09, 2011 1:18 PM by Steven Chen
    I think that in the mobile world (phones and tablets), UFS and SSIC (implemented with MIPI M-PHY and USB 3.0 link layer) will be very important. Both standards share the MIPI M-PHY, which allows a modular IP reuse approach to SoC design. UFS v1 is 3 Gbps which is screaming fast compared to eMMC at < 1 Gbps. And SSIC will allow 4.8 Gbps USB 3.0 connections. So both standards will allow fast, high bandwidth connections to flash and peripherals. Where they will have issues is latency, but that is what C2C and LLI are for. 
    eSATA is big in PCs and set top boxes and will continue to be, with the requirement being driven by the HD manufacturers. I'm not sure if we'll ever see eSATA on a phone or tablet once UFS and huge capacity flash cards are ubiquitous. 
    One place I go to keep up on connectivity standards, especially the MIPI ones, is Hezi Saar's blog at Synopsys at Also, Eric Esteve offers MIPI market research reports at and writes interesting articles at 
    Posted @ Tuesday, August 09, 2011 2:01 PM by Kurt Shuler
    Thanks for the helpful links Kurt! I agree with you on eSATA. With the the adoption of SSIC and especially UFS (which allows daisy chain), there is low need for eSATA in mobile interchip connectivity. Comparing between SSIC and UFS alone, I am not sure how well SSIC will play out since it is bottle-necked at 4.8Gbps. What is the loyalty associated with these standards? 
    I came across an interesting article, which talks about PCIe as an interchip interface. ( How do you see PCIe will play out in the mobile interchip space, leveraging its success in PCs?
    Posted @ Thursday, August 11, 2011 1:26 PM by Steven Chen
    A good question, and one that we have been looking at. I think the answer for mobility splits into two segments: 
    1. For mobile phones, which have severe form factor and power constraints, it seems that the application processor vendors will want to have their chip-to-chip interconnect standards (re-)use the MIPI M-PHY. SSIC and LLI were created with this requirement in mind. 
    2. Things get more interesting in the tablet market, where there are fewer size and power constraints and where some of the AP vendors have "PC DNA" in their blood. In this space, PCIe might be practical. 
    The problem for interchip connectivity always devolves to, "What are the interfaces I am connecting to?" (chicken and egg dilemma) and "What are my constraints?" (Power and form factor are the biggies here). My intuition tells me that if successful tablets continue to be "big smart phones", then the winning standards will use the MIPI M-PHY on the analog side of things. But this is only an opinion backed by minimal facts!
    Posted @ Thursday, August 11, 2011 2:01 PM by Kurt Shuler
    Indeed great summary.  
    How about power consumption (core+IO) between LLI and C2C?  
    Where do I license this C2C controller? (Arteris or TI?)  
    To connect C2C with OMAP4 and/or OMAP5, do I need 1.8V or 1.2V IOs?
    Posted @ Monday, September 05, 2011 3:43 AM by Arthur Lee
    I don't have any numbers on hand, but I expect LLI will have higher power consumption because of the M-PHY. 
    You can license the C2C controller from Arteris. Drop me an email if you want talk. 
    OMAP4 and OMAP5 can do 1.2V or 1.8V. This is true for most of the application processors we have worked with. Modem vendors usually make a choice between 1.2 or 1.8V. 
    I hope this helps! 
    Posted @ Wednesday, September 07, 2011 7:10 PM by Kurt Shuler
    Hi Kurt and Arthur, to follow up with your discussion on C2C and LLI, I see two main differences between them.  
    1. LLI requires M-PHY, while C2C does not require any PHY. As a result, LLI is expected to consume more power than C2C. (As Kurt said) 
    2. While LLI requires less pins, it requires existing modem or companion device makers to undergo device changes and adopt M-PHY. In contrast, C2C signals are carried through LPDDR IOs, which are already widely adopted in modems. Hence even though C2C use more pins, it is appealing for modem makers due to quicker/cheaper implementation.  
    Please give me a shout if I am misunderstanding these.  
    In addition, we now know a lot of standards builts on M-PHYs (LLI, UniPro, UFS, GBT, SSIC). To implement them on a single device, do we need separate M-PHY for each standards? or can they all share a single M-PHY and taking individual lanes? 
    Posted @ Thursday, September 08, 2011 1:33 PM by Steven Chen
    In response to latest comment made by Steven Chen (Sep 8, 1:33PM) 
    From system perspective I am not sure that C2C is really lower power than LLI for a given throughput. LLI use of Serdes technology allows to have lower voltage swing, reducing active power and EMI. LLI which is based on M-PHY allows to address the challenges in mobile space of: # of pins, power, EMI, scalability.  
    To your question about M-PHY, you can instantiate M-PHY to support different applications if the M-PHY was designed accordingly. To be practical you'll need a dedicated M-PHY per each protocol, however you can choose to multiplex between protocols assuming it's done wisely. 
    From the IP re-use perspective it just makes sense for modem or SoC designs to use M-PHY for different functions and use a widely adopted standard backed by MIPI alliance members such as LLI and DigRFv4 (in the model case). 
    Posted @ Thursday, September 08, 2011 2:09 PM by Hezi Saar
    Steven, Hezi,  
    Concerning the power comparison between C2C and LLI M-PHY based solution it will really depend on the application and the required throughput.  
    C2C implement a mechanism to dynamically turn on and off both the transmission clocks and the pads when no traffic is going through, this is why it definitely is very low power.  
    For the LLI solution, depending on what each M-Phy provider will design we expect power consumption to vary quite a bit, so it is hard as of today to do an estimate of the power consumption for M-Phy based solution.  
    But what is sure is that for modem-AP type of traffic, the C2C solution is very attractive from a power, ease of integration and re-usability of the already available DDR pads for modem guys. (I can hear the AP designers screening about their pad budget reading my post).  
    We can see with the market penetration of the C2C that the modem designers have chosen their camp for now. This might change in the years to come when more M-Phy solution will be available and that pin budget will become unbearable for AP teams.  
    At the end of the day, even if AP teams are trying to reduce their costs, modem teams are under even higher pressure due to the very low bill of material and price competition they are under, so even a few extra serdess (they have to keep the DDR for standalone mode) are out of the question for now. No doubt that support for even higher bandwidth needed for future wireless standards will push them over the bridge and go for LLI.  
    Maybe also if someone could promote DRAM connection based on serdess technology (and why not M-Phy), to reduce pin count again since I doubt that everybody could afford wide I/O TSV, then the modem team could again see a very appealing solution with the LLI.
    Posted @ Friday, September 16, 2011 1:54 PM by xavier leloup
    I think the HSI require a PHY opposed to what is mentioned in the table.
    Posted @ Tuesday, April 10, 2012 5:56 AM by Anirudh Gargi
    Thank you Anirudh! I updated the table in this article and created a separate article with the new table so others can find it easily.
    Posted @ Tuesday, April 10, 2012 11:10 AM by Kurt Shuler
    Hi, Kert 
    Do you have the datasheet/specification of C2C and MIPI-HSI ? 
    I am eager for those two specifications. 
    If you have, would you kindly send them to my mailbox? 
    My mailbox is '' . 
    Thanks a lot. 
    Posted @ Monday, October 22, 2012 3:51 AM by xiangpei
    I would like to cite this article in a scientific paper, however, blog entries are not really good references. Any intention to turn it at least into a "Technical Note", or similar, something that has a "number/year" etc.?
    Posted @ Wednesday, January 30, 2013 8:36 AM by Andreas Doering
    First of all , this blog post is one of the only one that talks about the various inter chip technologies in such clean and comparative manner.  
    I also read about the PCIe as a upcoming technology for these type of demands. PCIe can be successful taking its stable history with PC APs and the fact that soon all laptop architectures to have some kind of CP's (chrome pixel to start with, built in LTE). So great future on laptop board (maybe intel based tablets also) 
    As of now major vendor for CP lie on HSIC and HSI which can easily cater the speeds of Cat3/Cat4(only HSIC) of LTE. So until we have speeds more than Cat4 i see no immediate need, with SSIC also i guess mobile based AP ( mainly ARM based) , PCIe possibility on mobile and tablets will be dim.
    Posted @ Sunday, April 14, 2013 7:38 AM by Anirudh Gargi
    Thanks everyone for the feedback on this article. When I get the time I'd like to write another one that adds MIPI LLI-2, Mobile PCI Express (M-PCIe) and SuperSpeed Inter-Chip (SSIC). I'd love to get some power numbers (digital controller plus PHY) for these interfaces, but those seem really hard to get. 
    I may write this up as a downloadable white paper as per Andreas' suggestion. Depends on how much time I can set aside for this. The bulk of Arteris' business is on-chip interconnect fabric IP. The inter-chip connectivity IP is a smaller segment of our product line.
    Posted @ Wednesday, August 07, 2013 3:38 PM by Kurt Shuler
    Guys, thanks a lot for data! It might be useful in my work!
    Posted @ Sunday, September 08, 2013 8:16 AM by paperleader
    For C2C, is the need for DDR pads just because the operating freq. is 200MHz? Can it run at 100MHz, with non DDR pads?
    Posted @ Thursday, October 24, 2013 12:21 PM by Rabindra Guha
    C2C was designed and verified at 200 MHz. I can not assure you of correct operation at 100 MHz. If your chip need not conform to one of these industry standard interfaces, please let me tell you about other configurable inter-chip interface IP from Arteris.
    Posted @ Friday, October 25, 2013 3:41 PM by Jonah Probell
    It requires 1.2 or 1.8 volts and has throughput of 6.4 Gb/sec at 200 MHz DDR speeds and using 16 pins. is bubblegum casting legitimate
    Posted @ Monday, March 31, 2014 2:52 AM by tracypaulaa
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    Posted @ Thursday, April 03, 2014 4:47 AM by Kostenlos Haushaltstipps
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    Posted @ Thursday, April 17, 2014 2:06 AM by william gomes
    I would like to cite this article in a scientific paper, however, blog entries are not really good references. Any intention to turn it at least into a "Technical Note", or similar, something that has a "number/year" etc.?
    Posted @ Thursday, June 05, 2014 2:01 AM by harryellen
    Harry, sorry late getting back to you. Was on paternity vacation. 
    For the latest info that you can cite, I suggest downloading the vendors' white papers. Both Synopsys and Cadence have white papers on these topics. I don't have any intention to make this into a tech note or white paper.
    Posted @ Monday, June 16, 2014 4:33 PM by Kurt Shuler
    Excellent site I have bookmarked your site. Thanks
    Posted @ Thursday, August 07, 2014 10:54 PM by Kizi
    Compatibility is a big factor. Learning what hardware to install especially chipsets are important.
    Posted @ Monday, December 15, 2014 11:40 AM by
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