MIPI LLI Webinar on EE Times, Wednesday, 27 June
Hezi Saar (Synopsys' M-PHY PM), Philippe Martin (Arteris Senior Fellow and LLI God) and I will be hosting an EE Times webinar on the MIPI Low Latency Interface (MIPI LLI) and M-PHY on Wednesday, 27 June, at 9 am Pacific time.
You can sign up here:
This webinar will be technically "meaty" and it will NOT be a fluffy commercial for the Arteris / Synopsys joint LLI solution. The purpose of the LLI webinar is to show the real-world activites required to configure and integrate LLI into an SoC.
Here's the agenda for the webinar:
- MIPI LLI and M-PHY: Enabling Low Latency Companion Chip Use Cases
- LLI Implementation Best Practices
- Interfacing LLI to the System-on-Chip Interconnect
- Sizing and Setting up the M-PHY
- Addressing SoC integration challenges
- Summary Q&A
We'll have some slideware, but also a live demonstration showing things like how to configure AXI ports, address translation, sideband signal and interrupt management, determining the number of M-PHY LANES and GEAR speeds, configuring buffers, managing clock and power domains, reset and unmount, etc.
Lots of information in 1 hour!
We hope you can join us. Just click here.
BTW, here's the official overview of the webinar.
When designing mobile devices, it is critical to implement technologies that will future-proof your design, minimize BOM costs and board space, and maintain or improve performance. The MIPI Alliance Low Latency Interface (LLI) and M-PHY are two technologies that can help future-proof your design while giving it competitive advantages in terms of cost, board space, performance, and time-to-market.
The webinar will present a case study describing how LLI can be used to minimize DRAM footprint on a mobile phone system board. Particular attention will be paid to real-world implementation issues, such as clock domain, power and voltage management as well as integration with SoC interconnect fabrics.
This webinar will teach you:
- What the LLI and M-PHY technologies are, and best practices for implementation
- How LLI is different than other chip-to-chip interface standards, such as USB and PCIe
- How the LLI point-to-point interconnect can benefit multi-chip systems
- How the LLI controller and M-PHY IP can reduce the silicon footprint on your board
- How LLI can reduce individual BOM and multi-product platform costs