The 12-page technical paper, "Routing Congestion: The Growing Cost of Wires in Systems-on-Chip," by Arteris solutions architect Jonah Probell, uses experimental analysis and real-world examples to show how routing congestion affects semiconductor design and performance, and how it can be addressed with network on chip interconnect technology.
You will learn how:
- To reduce the number of wires required for AMBA AXI by 50%
- To calculate routing congestion
- Current SoC trends increase the likelihood of routing congestion
This concise paper explains everything the reader needs to know to make an initial assessment of routing issues within his or her current SoC projects.