Download this peer-reviewed IEEE technical paper to learn how:

• NoC interconnect technology has better idle and dynamic power dissipation than traditional busses or crossbars.
• NoC technology lowers power consumption while simultaneously meeting latency and bandwidth requirements.

Abstract

In this paper authors Diederik Verkest (IMEC), Dragomir Milojevic (Université Libre de Bruxelles) and Luc Montperrus (Arteris S.A.) present a Multi-Processor System-on-Chip (MPSoC) platform with six computational and four memory nodes interconnected with Arteris Network-on-Chip (NoC) interconnect IP. The platform is dedicated for real-time video encoding applications for high resolution images (HDTV) and frame rates of up to 30fps.

Extensive experiments established the power dissipation models of all individual NoC components, i.e. network interfaces, routers and wires. Based on these power models and the NoC topology they built the power model of the complete NoC. Finally they derived the power dissipation of the NoC for MPEG4 simple profile encoder. The results show that depending on the image resolution the power dissipation of the communication infrastructure vary between 15 and 22mW, which is comparable with state of the art dedicated low-power implementations.