In this 17-slide presentation you will learn the trends that are driving wire routing congestion and how network on chip technology reduces the number of wires and therefore the likelihood of routing congestion.

This presentation contains over 25 graphs, charts and photos to explain technical concepts.

This presentation walks the reader through experimental results to show how:

• Interface complexity and the number of required interfaces is increasing routing congestion.
• Packetization and serialization of commands and data simplifies on chip interconnect fabrics.
• Place and route tools prove the benefits of network on chip interconnects.

This short presentation is a valuable aid to understanding SoC wire routing congestion and how network on chip interconnect fabrics resolve it.