The congestion of wires in the place and route (P&R) stage of chip design poses an increasingly significant challenge to creating low cost, high performance chip designs. High congestion requires an increased die size or more metal mask layers. Congestion also causes long wire routes that create new and unpredictable critical paths that affect signal integrity and timing closure.
As more IP blocks and cores are added to each generation of chips, the number of routes between cores grows by a squared ratio. This increases the problem of congestion. Expectedly, eliminating congestion has become a key concern for EDA tool vendors who have addressed the problem with physical synthesis tools.
To address the growing cost of wires, the capability to easily configure the widths of interconnection links enables a trade-off between data throughput and wires. For a majority of IP interconnections, this allows a large reduction in the number of long wires at the RTL stage, before synthesis.
This paper presents trends in technology, introduces packet based network-on-chip as a means of enabling configuration link widths, shows experimental results, and describes other benefits of packet-based interconnect networks.
The highest performance supercomputer as of this writing, China’s he GPU-based Tianhe-1A, has 202,752 heterogeneous cores (TOP500.Org, 2010). That’s a lot, but it’s still not enough for an accurate weather forecast. Why can’t the operator simply double the number of nodes in order to increase the performance? The answer is: Wires. Wires take up space between the processing nodes and disks; sending signals across long wires takes time; driving signals on wires consumes power; and connecting processing nodes for the best performance is complicated. Solving those problems is the science of supercomputers. Multicore SoCs present analogous problems.
To download the rest of this paper, please provide the following information: